Processors of network devices (e.g., routers, switches, etc.) encapsulate packets with one or more headers. Some headers are data bytes related to specific network protocols, such as Ethernet, Internet protocol version 4 (IPv4), Fibre Channel (FC), IEEE 802.1, etc. Flexibility and performance are two criteria required for encapsulating packets with headers. Typically, packet header encapsulation is achieved using specially designed micro-code driven engines that execute a sequence of instructions to process packet headers. However, micro-coded engines present several challenges, such as performance limitations (e.g., time taken to process a packet is directly proportional to the number of instructions executed), micro-code memory requirements, complexity, protracted development schedules, etc. For example, a micro-coded engine will be an over-design when the set of protocol headers is somewhat pre-defined and an amount of flexibility required is bound by the processor's application space. In another example, if the processor's port rates are high, a micro-coded engine may become overly complex and may be unable to handle the high port rates.